This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating vertical surround gate structures in a semiconductor device array.
In semiconductor device applications, conventional planar transistors have the most mature integration process. However, in memory applications, particularly access devices (or selectors), reduction of device footprint is essential to improve memory density. Planar transistor performance is generally restricted by channel width and length. Reducing channel width or length can improve memory density at the cost of degraded device performance.
Thus vertical surround gate devices have become more attractive for such memory applications. In vertical surround gate devices the current flow is oriented in a vertical direction, providing many advantages to area efficiency. However, current reliable integration processes of vertical surround gate devices are relatively complex and expensive. In addition, in many applications, it is desirable to make the processes compatible with standard planar CMOS processes.